OpenMP Runtime
tomp_config.h
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00001 /*
00002  * Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
00003  *   All rights reserved.
00004  *
00005  *  Redistribution and use in source and binary forms, with or without
00006  *  modification, are permitted provided that the following conditions are met:
00007  *      * Redistributions of source code must retain the above copyright
00008  *        notice, this list of conditions and the following disclaimer.
00009  *      * Redistributions in binary form must reproduce the above copyright
00010  *        notice, this list of conditions and the following disclaimer in the
00011  *        documentation and/or other materials provided with the distribution.
00012  *      * Neither the name of Texas Instruments Incorporated nor the
00013  *        names of its contributors may be used to endorse or promote products
00014  *        derived from this software without specific prior written permission.
00015  *
00016  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
00019  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
00020  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
00021  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
00022  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
00023  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
00024  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
00025  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
00026  * POSSIBILITY OF SUCH DAMAGE.
00027  */
00028 
00034 #ifndef _TOMP_CONFIG_H_
00035 #define _TOMP_CONFIG_H_
00036 
00037 #include <stdint.h>
00038 
00044 typedef struct _tomp_CoreConfig
00045 {
00047     uint8_t     master_core_idx;
00048 
00050     uint8_t     num_cores;
00051 
00053     uint8_t     hw_sem_base_idx;
00054 
00056     uint8_t     thread_stack_from_heap;
00057 
00059     uint32_t    thread_stack_size;
00060 
00062     uint32_t     clock_freq;
00063 
00065     uint8_t     init_qmss;
00066 
00068     uint8_t     updateDP;
00069 
00073     int32_t     qmss_hw_queue_base_idx;
00074     uint32_t    qmss_first_desc_idx_in_linking_ram;
00075 
00079     uint32_t    qmss_first_memory_region_idx;
00080 } tomp_CoreConfig;
00081 
00082 
00083 extern tomp_CoreConfig    tomp_gvCoreConfig;
00084 
00085 
00086 /*
00087  * CORE CONFIGURATION
00088  */
00089 
00091 #define TOMP_NUM_CORES  (tomp_gvCoreConfig.num_cores)
00092 
00094 #define TOMP_MASTER_CORE_IDX (tomp_gvCoreConfig.master_core_idx)
00095 
00097 #define TOMP_CLOCK_FREQ_IN_HZ (tomp_gvCoreConfig.clock_freq * 1.0e6)
00098 
00102 #define TOMP_UPDATE_DP        (tomp_gvCoreConfig.updateDP)
00103 #define TOMP_MUST_UPDATE_DP   (tomp_gvCoreConfig.updateDP == 1)
00104 
00105 /*
00106  * QUEUE/LINKING RAM CONFIGURATION
00107  */
00108 
00109 #define TOMP_HW_QUEUE_NUM            (11)
00110 #define TOMP_MUST_INIT_QMSS          (tomp_gvCoreConfig.init_qmss == 1)
00111 #define TOMP_INIT_QMSS               (tomp_gvCoreConfig.init_qmss)
00112 
00117 #define TOMP_HW_QUEUE_BASE_IDX      (tomp_gvCoreConfig.qmss_hw_queue_base_idx)
00118 
00119 #define TOMP_QMSS_FIRST_DESC_IDX_IN_LINKING_RAM   \
00120                         (tomp_gvCoreConfig.qmss_first_desc_idx_in_linking_ram)
00121 #define TOMP_QMSS_FIRST_MEMORY_REGION_IDX         \
00122                         (tomp_gvCoreConfig.qmss_first_memory_region_idx)
00123 
00124 
00125 /*
00126  * HARDWARE SEMAPHORE CONFIGURATION  (6 semaphores required)
00127  */
00128 
00133 #define TOMP_ATOMIC_HW_SEM_IDX         (tomp_gvCoreConfig.hw_sem_base_idx)
00134 
00136 #define TOMP_CRITICAL_HW_SEM_IDX      (tomp_gvCoreConfig.hw_sem_base_idx + 1)
00137 
00139 #define TOMP_WS_HW_SEM_IDX      (tomp_gvCoreConfig.hw_sem_base_idx + 2)
00140 
00142 #define TOMP_TASK_HW_SEM_IDX    (tomp_gvCoreConfig.hw_sem_base_idx + 3)
00143 
00145 #define TOMP_MALLOC_HW_SEM_IDX  (tomp_gvCoreConfig.hw_sem_base_idx + 4)
00146 
00148 #define TOMP_LOCK_HW_SEM_IDX    (tomp_gvCoreConfig.hw_sem_base_idx + 5)
00149 
00151 #define QMSS_HW_SEM             (tomp_gvCoreConfig.hw_sem_base_idx + 2)
00152 
00153 
00154 #define TOMP_THREAD_STACK_IN_L2 (tomp_gvCoreConfig.thread_stack_from_heap == 0)
00155 
00156 #endif /*  _TOMP_CONFIG_H_ */
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