OpenMP Runtime
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tomp_config.h File Reference

Defines the configuration structure used by the OpenMP runtime. More...

#include <stdint.h>
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Classes

struct  tomp_CoreConfig

Defines

#define TOMP_NUM_CORES   (tomp_gvCoreConfig.num_cores)
#define TOMP_MASTER_CORE_IDX   (tomp_gvCoreConfig.master_core_idx)
#define TOMP_CLOCK_FREQ_IN_HZ   (tomp_gvCoreConfig.clock_freq * 1.0e6)
#define TOMP_UPDATE_DP   (tomp_gvCoreConfig.updateDP)
#define TOMP_MUST_UPDATE_DP   (tomp_gvCoreConfig.updateDP == 1)
#define TOMP_HW_QUEUE_NUM   (11)
#define TOMP_MUST_INIT_QMSS   (tomp_gvCoreConfig.init_qmss == 1)
#define TOMP_INIT_QMSS   (tomp_gvCoreConfig.init_qmss)
#define TOMP_HW_QUEUE_BASE_IDX   (tomp_gvCoreConfig.qmss_hw_queue_base_idx)
#define TOMP_QMSS_FIRST_DESC_IDX_IN_LINKING_RAM   (tomp_gvCoreConfig.qmss_first_desc_idx_in_linking_ram)
#define TOMP_QMSS_FIRST_MEMORY_REGION_IDX   (tomp_gvCoreConfig.qmss_first_memory_region_idx)
#define TOMP_ATOMIC_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx)
#define TOMP_CRITICAL_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 1)
#define TOMP_WS_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 2)
#define TOMP_TASK_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 3)
#define TOMP_MALLOC_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 4)
#define TOMP_LOCK_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 5)
#define QMSS_HW_SEM   (tomp_gvCoreConfig.hw_sem_base_idx + 2)
#define TOMP_THREAD_STACK_IN_L2   (tomp_gvCoreConfig.thread_stack_from_heap == 0)

Variables

tomp_CoreConfig tomp_gvCoreConfig
 Configuration structure.

Detailed Description

Defines the configuration structure used by the OpenMP runtime.


Define Documentation

#define QMSS_HW_SEM   (tomp_gvCoreConfig.hw_sem_base_idx + 2)

Reuse OMP runtime WS/TASK semaphores. Check with FM on overlap

#define TOMP_ATOMIC_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx)

General purpose hardware semaphore

  • used for atomic increment/decrement on runtime variables
  • mutual exclusion in atomic regions
#define TOMP_CLOCK_FREQ_IN_HZ   (tomp_gvCoreConfig.clock_freq * 1.0e6)

Clock frequency of the cores in Hertz

#define TOMP_CRITICAL_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 1)

Ensures mutual exclusion in critical regions

#define TOMP_HW_QUEUE_BASE_IDX   (tomp_gvCoreConfig.qmss_hw_queue_base_idx)

OEM: QMSS general purpose queue base index for the application event pools. These queues store the free events before they are allocated by the runtime.

#define TOMP_LOCK_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 5)

Ensures mutual exclusion when accessing lock variables

#define TOMP_MALLOC_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 4)

Used solely to ensure mutual exclusion for malloc/free

#define TOMP_MASTER_CORE_IDX   (tomp_gvCoreConfig.master_core_idx)

Index of the master core

#define TOMP_NUM_CORES   (tomp_gvCoreConfig.num_cores)

Number of cores participating in the runtime

#define TOMP_TASK_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 3)

Ensures mutual exclusion when accessing tasking related variables

#define TOMP_UPDATE_DP   (tomp_gvCoreConfig.updateDP)

If update DP is 1, runtime will update DP for worker cores before dispatching implicit tasks

#define TOMP_WS_HW_SEM_IDX   (tomp_gvCoreConfig.hw_sem_base_idx + 2)

Ensures mutual exclusion when accessing worksharing related variables

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